In this paper we have investigated the effect of device geometry parameters on junctionless transistor’s (JLTs) electrostatic characteristics. Emphasis is given on variation in gate length, gate oxide thickness and channel doping concentration to understand the scalability of JLT. Critical properties like threshold voltage, subthreshold swing, transconductance are evaluated for down scaled JLT structures to understand the optimization of device parameters. Low gate oxide thickness and apposite doping concentration is required to fully deplete the channel and maintain high current, respectively.

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