In this SPICE simulation study, we systematically analyzed the speed and reliability performance of RTFF (Input-aware pre-charge retentive true single phase clocked flip-flop), REFF (Redundancy eliminated flip-flop) and SSPL (Self-shut off pulsed latch) D-flip flops (FFs) with 16 nm CMOS process with a V_DD range from 0.7 V to 1 V at wide operating temperature (27 °C to 107 °C). The RTFF, REFF and SSPL showcased a power consumption of 4.803/11.67/15.97/24.34 µW, 4.996/8.671/12.95/19.9 µW, and 3.746/7.762/14.62/26.22 µW, respectively at a V_DD of 0.7/0.8/0.9/1.0 V at 27 °C. Similarly, RTFF, REFF and SSPL exhibited a D-Q delay (DQD) of 15.7/15.47/13.51/6.611 pS, 15.33/12.18/10.48/9.239 pS, and 37.13/26.1/21.04/23.45 pS, respectively, at a V_DD of 0.7/0.8/0.9/1.0 V at 27 °C. The RTFF, REFF and SSPL have shown a power consumption of 4.194/9.702/12.24/22.16 µ W, 4.281/6.853/11.17/17.47 µW, and 3.389/6.125/8.513/21.54 µW, respectively, at a V_DD of 0.7/0.8/0.9/1.0 V at 107 °C. On the other hand, RTFF, REFF and SSPL exhibited a DQD of 22.67/21.6/19.53/9.537 pS, 21.53/16.69/13.99/12.23 pS, and 56.2/35.24/27.8/23.45 pS, respectively, at a V_DD of 0.7/0.8/0.9/1.0 V at 107 °C. These D-FFs are considered as most promising for future self-powered or battery-operated internet of things devices and portable devices such as tablets, mobiles, laptops, smart phones, and similar handheld devices.

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