This paper studies the scalability and thermal reliability of Positive/Negative Edge Triggered type True Single Phase Clock-D Flip Flops (PET/NET-TSPCDFFs) implemented using 16 nm, 22 nm, 32 nm and 45 nm CMOS processes with a V_DD (supply voltage) of 0.7 V, 0.8 V, 0.9 V and 1 V, respectively. Less transistor count and clock signal with single phase are the unique features of PET/NET-TSPC-DFFs. PET-TSPC-DFFs designed with 16 nm (V_DD = 0.7 V), 22 nm (V_DD = 0.8 V), 32 nm (V_DD = 0.9 V), and 45 nm (V_DD = 1 V) CMOS processes showcased an average power consumption of 3.019 (2.823) µW, 5.403 (4.747) µW, 10.98 (9.679) µW and 20.76 (17.89) µW at 27 °C/107 °C, respectively, and an average DQD (D-to-Q-Propagation Delay) of 12.52 (17.45) pS, 13.88 (19.38) pS, 15.54 (21.7) pS, and 16.95 (23.98) pS, respectively. On the other hand, NET-TSPC-DFFs designed with 16 nm (V_DD = 0.7 V), 22 nm (V_DD = 0.8 V), 32 nm (V_DD = 0.9 V), and 45 nm (V_DD = 1 V) CMOS processes showcased an average power consumption of 5.841 (5.016) µW, 10.66 (9.158) µW, 21.70 (18.45) µW and 41.49 (35.50) µW at 27 °C/107 °C, respectively and an average DQD of 18.55 (27.59) pS, 21.41 (31.47) pS, 23.83 (34.47) pS, and 26.09 (37.96) pS, respectively.

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