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  Scopus ID: 21100926589

Response Analysis of a Polysilicon-NADGFET Inverter with High-k and Low-k Gate Oxide Materials at Sub-90 nm Regime: A TCAD Simulation

Banoth Vasu Naik and Arun Kumar Sinha

Abstract

In this paper response from an inverter at sub-90 nm regime, comprising of non-aligned double gate field effect transistors (NADGFETs) have been presented by replacing a gate oxide layer with the silicon dioxide (low-k, dielectric constant 3.8), and hafnium dioxide (HfO2) (high-k, dielectric constant 24). The simulation results are presented using a 2-Dimensional simulation in TCAD environment. The transient response, current consumption, and voltage transfer characteristics (VTC) are presented along with the total power dissipation. The inverter is applied with extreme high frequency i.e., 10 GHz, and has load capacitor of 10 femto-Farad value. It is observed that inverter gives rise time, fall time with low-k gate oxide as, 14.5 picosecond (ps), 7.89 ps, and with high-k gate oxide as, 16.3 ps, 8 ps, respectively. The total power consumption is 0.463 mW, and 0.525 mW, for low-k and high-k gate oxide, respectively. The VTC shows the same switch point for the two gate oxides, hence the low-k material can be suitable gate oxide for a logic gate meant to work at extreme high frequencies.

Published on: December 21, 2023
doi: 10.17756/nwj.2023-s5-010
Citation: Naik BV, Sinha AK. 2023. Response Analysis of a Polysilicon-NADGFET Inverter with High-k and Low-k Gate Oxide Materials at Sub-90 nm Regime: A TCAD Simulation. NanoWorld J 9(S5): S52-S56.

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