This paper presents result from TCAD simulation of a proposed threedimensional (3D) non-aligned double-gate n-channel field effect transistor (NADGNFET device). The device has a junction and symmetrical structure with 50% non-alignment in gate placement and 40 nm channel length, giving improved results in various figures of merit used for calibrating nano devices. The device uses a high-k spacer of hafnium oxide (HfO₂) with dielectric constant of 24 placed under the polysilicon forming double gates on the two sides of the NADGNFET device. The device parameters extracted from input and output characteristics simulation were, threshold voltage (V_TH), small-signal transconductance (g_m), output conductance (g_ds), OFF current (I_OFF) and ON current (I_ON), total gate capacitance (C_GG). Also, various analog figure of merit parameters like subthreshold swing (SS), drain induced barrier lowering, and intrinsic gain (A_VO) were measured. The radio frequency (RF) figure of merit parameters like, cut-off frequency (f_T), transconductance generation factor (TGF), and transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), along with linearity figure of merit like, intercepted input power-3 (IIP3) and intercepted intermodulation current-3 (IMD3), were plotted and measured. The simulation result shows the device achieved a good performance in various figures of merit when compared to the past works.

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