This paper discusses the optimization of the critical collector contact (CC) in compound semiconductor devices. It also addresses solutions to fundamental challenges including a robust procedure for detecting and minimizing process variation and drifts in the high-volume manufacturing environment. While insufficient alloying results in an incompletely formed collector contact, excessively high temperatures during or downstream from the alloy step results in undesirable diffusion. Run-to-run process variation was minimized, and intra-wafer heating uniformity was improved through dialing in the rapid thermal alloy process recipe and temperature profile as well as utilizing graphite susceptors for identical backside conditions for wafer processing. Implementation of a short loop for earlier electrical testing of collector parameters on process control monitor (PCM) structures after downstream oxidative and thermal treatments in the device fabrication flow had reduced the standard turnaround time by an average of 35%. This not only expedited recipe qualification procedures at a time-sensitive step but also enhanced statistical process control for production. As such, low collector contact resistance (R_C) was achieved; hence series resistance and impedance into the device were reduced.

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